1. Field of the Invention
The present invention relates generally to semiconductor memories, and more particularly, to a semiconductor memory having a data preset function. The present invention has particular applicability to digital signal processing LSI devices.
2. Description of the Background Art
A digital signal processing LSI device for processing digital signals has been known widely. For example, in the field of video signal processing, the digital signal processing LSI device for processing video data at a high speed is often used. The digital signal processing LSI device usually uses various memories such as a line memory, a field memory, or a frame memory. In order to configure these memories, a dynamic random access memory (hereinafter referred to as a "DRAM") is provided in the digital signal processing LSI device.
Generally, a conventional DRAM stores externally applied data and provides the stored data. Therefore, desired data is not stored without writing data, causing desired data not to be provided from the DRAM.
It is often necessary to set predetermined data in the digital signal processing LSI device. For example, in the field of video signal processing, in order to adjust a television receiver, predetermined data, that is, test data for indicating color bar or cross hatch is required. The conventional digital signal processing LSI device does not have a function of producing such predetermined data in itself, so that it is necessary to provide such data from an external circuit such as a CPU. In other words, an external device is required for supplying predetermined data to the digital signal processing LSI device; however, addition of such an external device incurs increase in scale and complication.
FIG. 17 is a schematic diagram of a circuit showing one example of a memory cell in the conventional DRAM. A memory cell 10 shown in FIG. 17 is disclosed in U.S. Pat. No. 4,935,869. Referring to FIG. 17, memory cell 10 includes a capacitor 14 for storing a data signal, and three NMOS transistors 11, 12 and 13. Transistor 11 is turned on in response to a signal on a write word line WW, and applies a data signal on a write bit line WB to capacitor 14. Transistor 12 is turned on or off in response to the data signal stored by capacitor 14. Transistor 13 is turned on in response to a signal on a read word line RW, and selectively pulls down a read bit line RB in accordance with the stored data signal.
In a data writing operation, the write word line WW is brought to a high level. Since transistor 11 is turned on, the data signal on the write bit line WB is applied to capacitor 14. In other words, capacitor 14 is charged or discharged by a signal charge on the write bit line WB.
When capacitor 14 is charged to a power supply voltage level (i.e. a high level), transistor 12 is brought to an on state in reading data. On the other hand, when capacitor 14 is discharged to a ground voltage level (i.e. a low level), transistor 12 is brought to an off state in reading data.
In a data reading operation, after the read bit line RB is precharged, the read word line RW is brought to a high level. Since transistor 13 is turned on, the potential of the read bit line WB is changed in accordance with the conductive state of transistor 12. In other words, when transistor 12 is turned on, the potential of the read bit line RB is pulled down through transistors 12 and 13. Conversely, when transistor 12 is turned off, the potential of the read bit line RB is not changed, that is, maintained. After conduction of transistor 13, by detecting the potential of the read bit line RB by a sense amplifier, not shown, the data signal stored in memory cell 10 is read out.
FIG. 18 is a schematic diagram of a circuit showing another example of a memory cell in the conventional DRAM. Referring to FIG. 18, a memory cell 20 includes a capacitor 23 for storing a data signal, and two NMOS transistors 21 and 22. Transistor 21 connects a first bit line BL1 to capacitor 23 in response to a signal on a first word line WL1. Similarly, transistor 22 connects a second bit line BL2 to capacitor 23 in response to a signal on a second word line WL2. In other words, memory cell 20 can be accessed through two access ports (not shown).
When memory cell 20 is accessed through a first access port, the word line WL1 is brought to a high level. Since transistor 21 is turned on, capacitor 23 is charged or discharged in accordance with the potential of the bit line BL1 in the writing operation. In the reading operation, after the bit line BL1 is brought to Vcc/2 in advance, the word line WL1 is brought to a high level. Therefore, the potential of the bit line BL1 is changed in accordance with an electric charge stored in capacitor 23. By detecting potential change of the bit line BL1 by a sense amplifier, not shown, the data signal stored in memory cell 20 is read out. On the other hand, data writing and data reading through a second access port can be carried out in the same manner as described above.
FIG. 19 is a schematic diagram of a circuit showing still another example of a memory cell in the conventional DRAM. Referring to FIG. 19, a memory cell 30 includes a capacitor 32 for storing a data signal, and an NMOS transistor 31. In the data writing operation, the word line WL is brought to a high level. Since transistor 31 is turned on, capacitor 32 is charged or discharged in accordance with the potential of the bit line BL. On the other hand, in the data reading operation, after the bit line BL is precharged to Vcc/2, the word line WL is brought to a high level. Since transistor 31 is turned on, the potential of the bit line BL is changed in accordance with the stored data signal. By detecting potential change of the bit line BL by a sense amplifier, not shown, the data signal is read out.
As shown in FIGS. 17, 18 and 19, conventional DRAM memory cells 10, 20 and 30 only store an applied data signal, and only provide the stored data signal. These memory cells 10, 20 and 30 are used in the above-mentioned digital signal processing LSI device, so that these memory cells cannot provide such data without writing predetermined data. This is also the case with a static random access memory (SRAM).